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Renesas Electronics /R7FA6M3AH /EPTPC0 /PDMACRL

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Interpret as PDMACRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PDMACRL

Description

PTP-pdelay Message MAC Address Setting Registers

Fields

PDMACRL

These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-pdelay messages.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data